Dr. Yogesh Kalidas Kirange, along with his co-inventors, successfully obtained the Registration of Design from the Patent Office, Government of India for the innovative design titled "Low Voltage Fault Detection Device." The design was registered under Design No. 490853-001 in Class 10-05, with the registration date 12 February 2026, and the certificate was issued on 24 March 2026. This achievement recognizes the originality and innovation of the design under the Designs Act, 2000, demonstrating the team's contribution to the development of advanced electrical fault detection technology for improved safety, reliability, and efficiency in electrical power systems.